The rapid growth of the semiconductor industry over the past three decades has largely been enabled by continual advancements in manufacturing technology which have allowed the size of the transistor, the basic building block in integrated circuits (ICs), to be steadily reduced with each new generation of technology. As the transistor size is scaled down, the chip area required for a given circuit is reduced, so that more chips can be manufactured on a single silicon wafer substrate, resulting in lower manufacturing cost per chip; circuit operation speed also improves, because of reduced capacitance and higher transistor current density. State-of-the-art fabrication facilities presently manufacture ICs with minimum transistor lithographically defined feature size smaller than 100 nm, so that microprocessor products with transistor counts approaching 100 million transistors per chip can be manufactured cost-effectively. High-density semiconductor memory devices have already reached the gigabit scale, led by dynamic random access memory (DRAM) technology. The DRAM memory cell consists of a single pass transistor and a capacitor (1T/1C), wherein information is stored in the form of charge on the capacitor. Although the DRAM cell provides the most compact layout (with area ranging between 4F2 and 8F2, where F is the minimum feature size), it requires frequent refreshing (typically on the order of once per millisecond) because the charge on the capacitor leaks away at a rate of approximately 10−15 Amperes per cell. This problem is exacerbated by technology scaling, because the transistor leakage current increases with decreasing channel length, and also because a reduction in cell capacitance results in a smaller number of stored charge carriers, so that more frequent refreshing is necessary. Thus, scaling of DRAM technology to much higher densities presents significant technological challenges.
Static RAM (SRAM) does not require refreshing and is generally faster than DRAM (approaching 1 ns access times as compared to tens of ns for DRAM). However, the SRAM cell is more complex, requiring either four n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and two p-channel MOSFETs, or four n-channel MOSFETs and two polycrystalline-silicon (poly-Si) load resistors, resulting in significantly larger cell size (typically greater than >120 F2). Innovations which provide significant reductions in SRAM cell size while allowing the SRAM cell to retain its favorable operating characteristics are therefore highly desirable.
Negative differential resistance (NDR) devices have previously been proposed for compact static memory applications. E. Goto in IRE Trans. Electronic Computers, March 1960, p. 25 disclosed an SRAM cell consisting of two resonant tunneling diodes (RTDs) and a pass transistor. For a variety of NDR devices including RTDs, the current first increases with increasing applied voltage, reaching a peak value, then decreases with increasing applied voltage over a range of applied voltages, exhibiting negative differential resistance over this range of applied voltages and reaching a minimum (“valley”) value. At yet higher applied voltages, the current again increases with increasing applied voltage. Thus, the current-vs.-voltage characteristic is shaped like the letter “N”. A key figure of merit for NDR devices is the ratio of the peak current to the valley current (PVCR). The higher the value of the PVCR, the more useful the NDR device is for variety of circuit applications. The PVCR of RTDs is generally not high enough to make it practical for low-power SRAM application, because in order for the RTDs in a Goto cell to have sufficient current drive, the valley current is too large, causing large static power dissipation. In addition, RTDs require specialized fabrication process sequences so that the complexity of an integrated RTD/MOSFET SRAM process would be substantially higher than that of a conventional complementary MOS (CMOS) SRAM process, resulting in higher manufacturing cost.
Accordingly, there exists a significant need for NDR devices with very high (>106) PVCR which can be easily integrated into a conventional CMOS technology, for compact, low-power, low-cost SRAM.
A new type of SRAM device to achieve such functionality using Negative Differential Resistance Field Effect Transistors (NDR FETs) is described in detail in U.S. Pat. No. 6,724,655, issued Apr. 20, 2004 to T. King and assigned to the present assignee. The NDR FET structure, operation, and method of making the same are discussed in detail in U.S. Pat. No. 6,512,274, issued Jan. 28, 2003 to King et al., which is also assigned to the present assignee. Such details are also disclosed in a corresponding PCT application PCT/US01/19825 which was published as publication no. WO 01/99153 on Dec. 27, 2001. The above materials are hereby incorporated by reference.
Additional embodiments of such device are clearly advantageous for use in memory applications, particularly embedded memory.